SMSC DS LPC47M112
Rev. 01/09/2001
LPC47M112-MC
Enhanced Super I/O Controller with LPC Interface
FEATURES
3.3 Volt Operation (5 Volt Tolerant)
LPC
Interface
ACPI 1.0 Compliant
Fan
Control
-
Fan Speed Control Outputs
-
Fan Tachometer Inputs
Programmable Wake-up Event Interface
PC98, PC99 Compliant
Dual Game Port Interface
MPU-401 MIDI Support
General Purpose Input/Output Pins
ISA Plug-and-Play Compatible Register Set
Intelligent Auto Power Management
System Management Interrupt
2.88MB Super I/O Floppy Disk Controller
-
Licensed CMOS 765B Floppy Disk Controller
- Software and Register Compatible with
SMSC's Proprietary 82077AA Compatible
Core
-
Supports Two Floppy Drives Directly
- Configurable Open Drain/Push-Pull Output
Drivers
-
Supports Vertical Recording Format
-
16-Byte Data FIFO
-
100% IBM Compatibility
-
Detects All Overrun and Underrun Conditions
- Sophisticated Power Control Circuitry (PCC)
Including Multiple Powerdown Modes for
Reduced Power Consumption
-
DMA Enable Logic
-
Data Rate and Drive Control Registers
-
480 Address, Up to Eight IRQ and Three DMA
Options
Enhanced Digital Data Separator
-
2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250
Kbps Data Rates
-
Programmable Precompensation Modes
Keyboard
Controller
- 8042
Software
Compatible
-
8 Bit Microcomputer
-
2k Bytes of Program ROM
256 Bytes of Data RAM
- Four Open Drain Outputs Dedicated for
Keyboard/Mouse Interface
-
Asynchronous Access to Two Data Registers
and One Status Register
-
Supports Interrupt and Polling Access
-
8 Bit Counter Timer
-
Port 92 Support
-
Fast Gate A20 and KRESET Outputs
Serial
Ports
-
Two Full Function Serial Ports
- High Speed NS16C550 Compatible UARTs
with Send/Receive 16-Byte FIFOs
-
Supports 230k and 460k Baud
Programmable Baud Rate Generator
Modem Control Circuitry
-
480 Address and 15 IRQ Options
Infrared
Port
-
Multiprotocol Infrared Interface
-
IrDA 1.0 Compliant
-
SHARP ASK IR
-
480 Addresses, Up to 15 IRQ
Multi-Mode Parallel Port with ChiProtect
-
Standard Mode IBM PC/XT, PC/AT, and PS/2
Compatible Bidirectional Parallel Port
- Enhanced Parallel Port (EPP) Compatible -
EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant)
-
IEEE 1284 Compliant Enhanced Capabilities
Port (ECP)
-
ChiProtect Circuitry for Protection
-
480 Address, Up to 15 IRQ and Three DMA
Options
LPC
Interface
-
Multiplexed Command, Address and Data Bus
- Serial IRQ Interface Compatible with
Serialized IRQ Support for PCI Systems
- PME
Interface
100 Pin QFP Package in a 3.2 mm format
SMSC DS LPC47M112
Page 2
Rev. 01/09/2001
80 Arkay Drive
Hauppauge,
NY
11788
(631)
435-6000
FAX (631) 273-3123
Copyright SMSC 2004. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC
or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard
Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.
SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause
or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further
testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale
Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems
Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.
IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES;
OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR
NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
SMSC DS LPC47M112
Page 3
Rev. 01/09/2001
GENERAL DESCRIPTION
The LPC47M112-MC* is a 3.3V (5V tolerant) PC98/PC99 compliant Super I/O controller. The LPC47M112-MC
implements the LPC interface, a pin reduced ISA bus interface which provides the same or better performance as the
ISA/X-bus with a substantial savings in pins used. The LPC47M112-MC provides fan control through two fan speed
control output pins and two fan tachometer input pins. It also provides 37 general purpose input/output (GPIO) pins, a
dual game port interface and MPU-401 MIDI support.
The LPC47M112-MC incorporates a keyboard interface, SMSC's true CMOS 765B floppy disk controller, advanced
digital data separator, two 16C550A compatible UARTs, one Multi-Mode parallel port which includes ChiProtect
circuitry plus EPP and ECP, on-chip 12 mA AT bus drivers, one floppy direct drive support, and Intelligent Power
Management including PME support. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and
PC/AT architectures in addition to providing data overflow and underflow protection. The SMSC advanced digital data
separator incorporates SMSC's patented data separator technology, allowing for ease of testing and use. Both on-
chip UARTs are compatible with the NS16C550A. The parallel port is compatible with IBM PC/AT architecture, as
well as IEEE 1284 EPP and ECP. The LPC47M112-MC incorporates sophisticated power control circuitry (PCC)
which includes support for keyboard and mouse wake-up events. The PCC supports multiple low power-down
modes.
The LPC47M112 supports the ISA Plug-and-Play Standard (Version 1.0a) and provides the recommended
functionality to support Windows '95, Windows 98, Windows 2000 and Windows ME.
The I/O Address, DMA Channel and hardware IRQ of each logical device in the LPC47M112-MC may be
reprogrammed through the internal configuration registers. There are 480 I/O address location options, a Serialized
IRQ interface, and three DMA channels.
The LPC47M112-MC does not require any external filter components and is therefore easy to use and offers lower
system costs and reduced board area. The LPC47M112-MC is software and register compatible with SMSC's
proprietary 82077AA core.
ORDERING INFORMATION
Order Number:
LPC47M112-MC for 100 Pin QFP Package
SMSC DS LPC47M112
Page 4
Rev. 01/09/2001
TABLE OF CONTENTS
FEATURES....................................................................................................................................................................1
GENERAL DESCRIPTION ............................................................................................................................................3
1
PIN CONFIGURATION...........................................................................................................................................6
2
DESCRIPTION OF PIN FUNCTIONS.....................................................................................................................7
2.1
Buffer Type Descriptions................................................................................................................................10
2.2
Pins That Require External Pullup Resistors .................................................................................................11
3
BLOCK DIAGRAM ...............................................................................................................................................12
4
REFERENCE DOCUMENTS................................................................................................................................13
5
3 VOLT OPERATION / 5 VOLT TOLERANCE ....................................................................................................14
6
POWER FUNCTIONALITY...................................................................................................................................15
6.1
VCC Power ....................................................................................................................................................15
6.2
VTR Support ..................................................................................................................................................15
6.3
Internal PWRGOOD ......................................................................................................................................15
6.4
32.768 kHz Trickle Clock Input ......................................................................................................................15
6.5
Indication of 32kHz Clock ..............................................................................................................................15
6.6
Trickle Power Functionality ............................................................................................................................15
6.7
VREF Pin .......................................................................................................................................................17
6.8
Maximum Current Values ..............................................................................................................................17
6.9
Power Management Events (PME/SCI).........................................................................................................17
7
FUNCTIONAL DESCRIPTION .............................................................................................................................18
7.1
Super I/O Registers .......................................................................................................................................18
7.2
Host Processor Interface (LPC) .....................................................................................................................18
7.3
LPC INTERFACE ..........................................................................................................................................18
7.4
Power Management.......................................................................................................................................20
7.5
LPC Transfer Sequence Examples................................................................................................................22
8
FLOPPY DISK CONTROLLER ............................................................................................................................23
8.1
FDC Internal Registers ..................................................................................................................................23
9
COMMAND SET/DESCRIPTIONS .......................................................................................................................39
10
INSTRUCTION SET..........................................................................................................................................41
11
SERIAL PORT (UART) .....................................................................................................................................58
12
Serial Data........................................................................................................................................................62
13
INFRARED INTERFACE ..................................................................................................................................70
14
MPU-401 MIDI UART........................................................................................................................................71
14.1
Overview ....................................................................................................................................................71
14.2
Host Interface.............................................................................................................................................71
15
Status Port .......................................................................................................................................................73
16
Bits[5:0] ............................................................................................................................................................74
16.1
MPU-401 Command Controller ..................................................................................................................75
16.2
MIDI UART.................................................................................................................................................76
16.3
MPU-401 Configuration Registers..............................................................................................................76
17
PARALLEL PORT ............................................................................................................................................77
17.1
IBM XT/AT Compatible, Bi-Directional And Epp Modes .............................................................................78
17.2
Extended Capabilities Parallel Port ............................................................................................................82
18
POWER MANAGEMENT..................................................................................................................................93
19
Timing Diagrams for SER_IRQ Cycle ............................................................................................................96
20
8042 KEYBOARD CONTROLLER DESCRIPTION..........................................................................................99
20.1
Latches On Keyboard and Mouse IRQs...................................................................................................104
20.2
Keyboard and Mouse PME Generation....................................................................................................106
21
GENERAL PURPOSE I/O...............................................................................................................................107
21.1
GPIO Pins ................................................................................................................................................107
21.2
Either Edge Triggered Interrupts ..............................................................................................................112
21.3
Led Functionality ......................................................................................................................................112
22
SYSTEM MANAGEMENT INTERRUPT (SMI) ...............................................................................................114
23
PME SUPPORT ..............................................................................................................................................115
SMSC DS LPC47M112
Page 5
Rev. 01/09/2001
23.1
`Wake On Specific Key' Option ................................................................................................................116
24
FAN SPEED CONTROL AND MONITORING ................................................................................................118
24.1
Fan Speed Control ...................................................................................................................................118
24.2
Fan Tachometer Inputs ............................................................................................................................119
25
SECURITY FEATURE ....................................................................................................................................122
25.1
GPIO Device Disable Register Control.....................................................................................................122
25.2
Device Disable Register ...........................................................................................................................122
26
GAME PORT LOGIC ......................................................................................................................................123
26.1
Power Control Register ............................................................................................................................124
26.2
VREF Pin .................................................................................................................................................124
27
RUNTIME REGISTERS ..................................................................................................................................125
28
CONFIGURATION ..........................................................................................................................................147
29
OPERATIONAL DESCRIPTION.....................................................................................................................163
29.1
Maximum Guaranteed Ratings* ...............................................................................................................163
DC ELECTRICAL CHARACTERISTICS ................................................................................................................163
30
TIMING DIAGRAMS .......................................................................................................................................166
31
PACKAGE OUTLINE......................................................................................................................................190
32
APPENDIX - TEST MODE ..............................................................................................................................191
32.1
Board Test Mode......................................................................................................................................191
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